As performance of semiconductor devices such as transistors, for example silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and/or various types of field-effect-transistors (FETs), continues to improve, demand for electric power or current supply by various types of semiconductor devices continues to increase. In general, electric current used by these semiconductor devices manufactured on a semiconductor chip are supplied through a set of electric interconnects which may act like a “power grid” of the semiconductor chip and therefore be referred to hereinafter like that. The power grid distributes electric power to various active semiconductor devices on the chip and is usually manufactured through processes commonly known as back end of the line (BEOL) technology. A power grid may spread across different conductive levels, including M1 level, M2 level, etc., and may in general provide electric power or current to the various semiconductor devices using conductive wires, paths, and/or pathways at different levels, and using vias and/or studs in crossing different levels, as is commonly known in the art.
FIG. 1A and FIG. 1B are demonstrative illustrations of a power grid structure, as is known in the art, that provides electric power to a semiconductor device. For example, semiconductor structure 100 may represent a portion or fraction of a large scale power grid that supplies electric power to one or more semiconductor devices manufactured on a single substrate. For example, semiconductor structure 100 may include a conductive stud 112 such as, for example, a CA contact stud that is formed on top of and in contact with a semiconductor device 102 that may be formed on a semiconductor substrate 101. Semiconductor structure 100 may also include a conductive wire, path, or pathway 122 such as, for example, an M1 level contact on top of and in contact with conductive stud 112, as being illustrated in FIG. 1A. Conductive stud 112 may be formed inside and/or through a dielectric layer 111, which may be for example an inter-level dielectric (ILD) layer. As is known in the art, generally a conductive liner 121 may be formed between M1 level contact of conductive path 122 and ILD layer 111, as well as at the sidewalls of M1 level, to reduce and/or eliminate potential metal contamination which may be caused by diffusion of metal element of conductive path 122 into ILD layer 111, and to increase and/or enhance adhesiveness of conductive path 122 to ILD layer 111. Further, a dielectric capping layer 131, for example a silicon nitride layer, may be formed on top of conductive path 122, upon which other ILD layer or layers (not shown) may be deposited to form additional metal level contacts. Similar to conductive liner 121, dielectric capping layer 131 may also serve the function of reducing metal contamination and/or improving isolation of conductive path 122.
FIG. 1B demonstratively illustrates that during normal operation of semiconductor device 102, electrons may flow from conductive stud 112 towards conductive path 122. Conductive stud 112 and conductive path 122 may be made of materials of different conductivity. In addition, current density at conductive stud 112 and conductive path 122 may be different due to different current levels and/or different cross-sectional areas thereof. Consequently, at a joint or intersection area 120 of conductive stud 112 and conductive path 122, electro-migration may occur and may manifest itself as causing or creating voids between conductive stud 112 and conductive path 122. The void created by electro-migration may gradually increase in size with the time of usage of semiconductor device 102, and may ultimately cause an open circuit at joint area 120 between conductive stud 112 and conductive path 122. In other words, electro-migration may create reliability concerns for semiconductor device 102 that employs a conventional power grid, like structure 100, for electric power supply. Such reliability concerns become particularly important when conductive path 122 is a M1 level contact.